VLSI Engineer — Signal Processing & Embedded Systems
I look for signal inside noise — from denoising passive sonar with autoencoders to keying hardware off the physical randomness of silicon at power-up. Comfortable across deep learning, CMOS design, and embedded systems.
UID 0x4D 45 48 44 45 45 50 — derived from name, ASCII-encoded, for illustration.
RAW SIGNAL → VARIATIONAL AUTOENCODER → CLEAN SIGNAL
Features
About
01
Cut self-noise in passive sonar signals using deep learning — a variational autoencoder with a custom STFT-based loss function reduced noise by 25%.
Designed and implemented an SRAM Physical Unclonable Function (PUF) authentication system, turning silicon power-up noise into a device-specific cryptographic key.
Comfortable across CMOS design (ring oscillators), Verilog cryptography (ChaCha20), and embedded IoT (ESP32-based home automation).
Completed industrial training in automation systems at the Baglihar Hydel Power Project, alongside an M.Tech in VLSI Design at Thapar Institute of Engineering & Technology.
Experience
Work History
02
01/2024 – 06/2024
Self-Noise Cancellation — Intern
IIT Jammu
Achieved self-noise cancellation in passive sonar using deep learning.
Reduced noise by 10% by improving an autoencoder, then by 25% with a variational autoencoder.
Cut the error rate by roughly e-10 using a custom STFT-based loss function.
Collaborated with the team to deliver required results.
06/2023 – 07/2023
Smart Home System — Intern
IIT Jammu
Implemented a smart home system using ESP32.
Built an automated fire and intruder detection system.
Created a web page to control home appliances.
Worked with DHT11, LDR, and PIR sensors.
Modules
Projects
03
M0108/2024 – 12/2024
SRAM PUF File Authentication System
Designed and implemented an SRAM Physical Unclonable Function using Arduino to generate hardware-unique keys.
Used intrinsic SRAM power-up states to create device-specific fingerprints for authentication.
Integrated the PUF response as a password mechanism for zip file encryption — eliminating stored or remembered keys.
M0202/2024 – 04/2024
Verilog Image Accelerator
Designed a Verilog-based approximate image accelerator.
Implemented a custom MAC unit for Canny edge detection.
Reduced power draw by ~15% and area by ~20%.
M0309/2024 – 12/2024
CMOS Ring Oscillator
Designed and implemented 3- and 5-stage CMOS ring oscillators using Mentor Graphics.
Compared frequency and propagation delay across configurations.
Showed the 3-stage design has comparatively lower delay.
M0402/2024 – 04/2024
ChaCha20 Encryption
Designed a Verilog implementation of the ChaCha20 encryption algorithm.